The accuracy of CMOS image sensor (CIS) is determined by the accuracy of single slope analog-to-digital (SS ADC) converter. As the DAC of single slope ADC, ramp generator plays an important role. The traditional on-chip global ramp generator circuit is greatly affected by process, voltage and temperature (PVT), resulting in ramp signal distortion and poor linearity, and due to parasitic effects, off-chip observation slope error is large, and calibration is difficult. This paper introduces a ramp generator which can resist PVT adaptive calibration slope. The ramp is fine-tuned by successive approximation algorithm and fine-tuned by fixed-step search method to realize two-point correction of slope. The circuit includes resistive mode DAC (RDAC), current mode DAC (IDAC), logic control, dynamic comparator and other modules. The average calibration period of the adaptive ramp generator is about 1.143ms.After calibration, the DNL of the adaptive ramp generator can reach +0.00207/-0.00115 LSB, the INL of the adaptive ramp generator can reach +0.6755/-0.3887 LSB, The calibration voltage error is less than 1.5 LSB and the power consumption is only 1.155mW under different PVT. It has the advantages of high precision and low power consumption.